A technique of reducing power consumption by cutting off a power voltage of some circuit blocks has been proposed. For example, when power of a static RAM (SRAM) is cut off stepwise using this technique, since data held in the SRAM disappears if the SRAM is powered off, it is necessary to move data in the SRAM to a non-volatile memory in advance, and thus power-off control is complicated. Further, a non-volatile memory for power-off is necessary in addition to the SRAM, and thus a circuit volume increases.
The SRAM can perform a high-speed operation, but an area per unit cell is large, and power consumption is also large. Furthermore, since the SRAM is a volatile memory, electric power is consumed even during standby.
In recent years, development of a high-speed non-volatile memory is in progress, and Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) or the like attracts attention. Some non-volatile memories such as the STT-MRAM are smaller in power consumption than the SRAM, but there are cases in which a plurality of power voltages are necessary for operation. Since a plurality of power voltages are not constantly used in a non-volatile memory, it is desirable to perform a certain power consumption reduction process.